Date: Mon, 17 Mar 1997 02:20:49 -0500 (EST) To: tghack-list@joyce.eng.yale.edu From: daves@interlog.com (David Shadoff) X-Software: MLF v2.3, Copyright 1995, 1996 by Bt X-Original-Id: <199703162311.SAA01025@smtp.interlog.com> Subject: Hu6270 Video controller info... X-UIDL: 19802eb6e87bc09bccbfde251c7c7df0 Ok... this is not complete, but it's a start: The Hu6270 video controller chip is a memory-mapped I/O chip, which creates the background and sprite graphics for the PC-Engine. There are 3 memory locations involved, all in segment $FF (hardware I/O segment): $0000 - Address/Status register $0002 - LSB of Data value $0003 - MSB of Data value The 'ST0', 'ST1', and 'ST2' opcodes are designed to quickly place 'immediate' addressing-mode data into each of the registers, respectively (ie. 'ST0' places data into $0000, etc...). The video memory is placed on the 6270's memory bus, which is *SEPARATE* from the Hu6280 CPU's bus. While the 6280's bus is 8 bits wide, the 6270's bus is 16 bits wide (thus, the LSB/MSB). There is 64KB of video RAM, located at memory locations $0000-$7FFF on the 6270's bus. Note that this is 32K *words* of memory. Additionally, there are several internal 16-bit 6270 video registers, used to control the display. The Address/Status register is called the 'Address' register when written to, and the 'Status' register when read from: Address register: Mask = $1F (Only the bottom 5 bits are used; all others ignored). The value placed here denotes what to do with the 16-bit value ($0002/$0003), when written. (see below) Status register: Different bits flag different conditions. Not all are known. The bitmap is as follows: '0abcdefg' 0 - always zero a - 'BSY' flag - I believethis is '1' when a DMA transfer is happening (although this is not completely clear at this time). b - 'VD' flag - I believe this is a '1' when Vertical Sync happens, otherwise a '0' (uncertain) c - 'DV' flag - (unknown) d - 'DS' flag - (unknown) e - 'RR' flag - I believe this is a '1' when Horizontal Sync happens, otherwise a '0' (uncertain) f - 'OR' flag - (unknown) g - 'CR' flag - (unknown) Table of Data Value Uses, by Address Register Values: Address Usage Data Value Register Name Used For 0 MAWR 'Memory Address Write Register' - this is the internal register used as an address-counter when writing to VRAM. All bits used (although no VRAM above $7FFF). 1 MARR 'Memory Address Read Register' - this is the internal register used as an address-counter when reading from VRAM. All bits used (although no VRAM above $7FFF). 2 VRR 'VRAM Read Register' - this is the only valid read-access from the data port. It reads the value from VRAM at the address specified by the MARR. When the value is read from the second byte-port at $0003, the MARR register (ie. the 'address to read from') is auto-incremented (although this may be a configurable behaviour). All bits used. 2 VWR 'VRAM Write Register' - (write-access version of the above) Write value to VRAM at the address specified by the MAWR. When the value is written to the second byte-port at $0003, the MAWR register (ie. the 'address to write to') is auto-incremented (although this may be a configurable behaviour). All bits used. 3 (unused) 4 (unused) 5 CR 'Control Register' - unclear, except that the 16-bit value is divided into the bitmap: '???aabccdeffgggg', where: ? = unused bit aa = 'IW' (unknown) b = 'DR' (unknown) cc = 'TE' (unknown) d = 'BB' (unknown) e = 'SB' (unknown) ff = 'EX' (unknown) gggg = 'IE' (unknown) This information is described in the Develo book, but it has not yet been translated. 6 RCR 'Raster Counter Register' - Use unknown at this time, although it is described in the Develo book. Mask = $03FF (bottom 10 bits are used). 7 BXR 'Background X-Scroll Register' - when the background map is a larger virtual size than the viewing screen shows, this is the viewing screen's x-offset (in pixels) from the origin of the virtual background map. Mask = $03FF 8 BYR 'Background Y-Scroll Register' - when the background map is a larger virtual size than the viewing screen shows, this is the viewing screen's y-offset (in pixels) from the origin of the virtual background map. Mask = $01FF Unfortunately, the Develo book does not mention much about the following registers: 9 MWR 'Memory-access Width Register' - Used to configure the size of the virtual background map. Not adequately described in the Develo book (from what I have seen), but they do give this bitmap: '????????abbbccdd', where: ? = unused bit a = 'CM' (unknown - presumably 'Color Mode') bbb = 'SCREEN' These bits control virtual map size as noted below cc = (unknown, unnamed) dd = (unknown, unnamed) From empirical evidence, I have noted that the 'SCREEN' bitmap is as follows: 000 = not a 'virtual' size; follow screen width settings from HDW (LSB of HSR). This is 32 tiles vertically, and usually 32 tiles or 40 tiles horizontally - a 'tile' is an 8x8-pixel character-generator-based block) 1xx = 'Y' axis virtual size = 64 tiles x01 = 'X' axis virtual size = 64 tiles x10 = (appears to be) 'X' axis virtual size = 128 tiles x11 = unknown, but appears to involve 'X' axis Mask = $00FF (MSB unused) 10 HSR 'Horizontal Sync Register' (?) - This is divided into two separate byte-sized registers; the MSB is called 'HDS' (purpose unknown), and the LSB is called 'HSW' (purpose unknown). Mask = $7F1F 11 HDR 'Horizontal Display Register' (?) - This is divided into two separate byte-sized registers; the MSB is called 'HDE' (purpose unknown), and the LSB is called 'HDW'. I have been able to infer that HDW (plus one) is the horizontal width of the display screen, in tiles. This is normally either $1F (+1 = $20; ie. 256 pixels) or $27 (+1 = $28; ie. 320 pixels). Mask = $7F7F 12 VPR (unknown) - This is divided into two separate byte-sized registers; the MSB is called 'VDS' (purpose unknown), and the LSB is called 'VSW' (purpose unknown). Probably deals with 'vertical' aspects of display-generation. Mask = $FF1F 13 VDW (unknown use) - Probably deals with 'vertical' aspects of display-generation. Mask = $01FF 14 VCR (unknown use) - Probably deals with 'vertical' aspects of display-generation. Mask = $00FF 15 DCR 'DMA Control Register' - unfortunately, there is not much information about this register (except a bitmap). Presumably, this register controls the actual DMA transfer, once the addresses have been set up. The text speaks of VRAM-VRAM DMA transfers, and VRAM-SATB DMA transfers (presumably, the sprite attribute table has a 'snapshot' taken each vertical-sync cycle, to maintain the integrity of the generated picture). The bitmap looks like: '???????????abcde', where: a - 'DV' flag (unknown) b - 'DS' flag (unknown) c - 'RR' flag (unknown) d - 'OR' flag (unknown) e - 'CR' flag (unknown) Mask = $001F 16 SOUR '(DMA) Source Register' - This register sets the source address for DMA transfers. All bits used (address pointer). 17 DESR '(DMA) Destination Register' - This register sets the destination address for DMA transfers. All bits used (although no VRAM above $7FFF). 18 LENR '(DMA) Length Register' - This register sets the length of the DMA transfer. All bits used (although no VRAM above $7FFF). 19 SATB 'Sprite Attribute Table' - This register points to the start address of the sprite attribute table. All bits used (although no VRAM above $7FFF). -- Dave --- TGHack List Information ------------------------------------------- Looking for TGHack list files? Visit our ftp site! You'll find sample code, disassemblers, mapping information, FAQs, and other goodies at ftp://joyce.eng.yale.edu/pub/TGHack. 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