
                     "PC Engine Video Display Controller"
                     ====================================



    1/ VDC I/O ports
       -------------

        The VDC can be accessed through 2 16-bit I/O ports in the hardware
        page (bank $FF):


        +-------+-----+------+---------------------------------------------+
        | $0000 | R/  |  SR  | Status Register                             |
        +-------+-----+------+---------------------------------------------+

                Bit 06 : 'BSY' Memory busy flag, indicates that the
                               VRAM is being read/written by the VDC
                               in response to a CPU request (VRR/VWR).

                Bit 05 : 'VD'  Vertical blanking flag.

                Bit 04 : 'DV'  VRAM DMA end of transfer flag, set to
                               indicate the end of a VRAM to VRAM
                               DMA transfer.

                Bit 03 : 'DS'  VRAM to SATB end of transfer flag.

                Bit 02 : 'RR'  Scanline interrupt flag.

                Bit 01 : 'OR'  Sprite overflow flag, set whenever
                               the sprite data could not be fetched,
                               usualy when there are more than 16
                               sprites on a scanline.

                Bit 00 : 'CR'  Sprite collision flag, set when
                               sprite #0 is in collision with any
                               other sprites.


        +-------+-----+------+---------------------------------------------+
        | $0000 |  /W |  AR  | Address Register                            |
        +-------+-----+------+---------------------------------------------+

                Bit 04-00 : VDC register index (0-19).


        +-------+-----+------+---------------------------------------------+
        | $0002 | R/W |  DR  | Data Register                               |
        +-------+-----+------+---------------------------------------------+

                bit 15-00 : Data to be read/written to a VDC register.


    2/ VDC registers
       -------------

        The VDC has a total of 20 16-bit registers (although 2 are reserved
        and should not be used, those are registers 3 & 4).


        +----+-----+------+------------------------------------------------+
        | $0 |  /W | MAWR | Memory Address Write Register                  |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : VRAM write pointer, set this register to the VRAM
                            location you want to change and write the new
                            data in VWR.


        +----+-----+------+------------------------------------------------+
        | $1 |  /W | MARR | Memory Address Read Register                   |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : VRAM read pointer, set this register to the VRAM
                            location you want to read and read the data in
                            VRR.


        +----+-----+------+------------------------------------------------+
        | $2 | R/  | VRR  | VRAM Read Register                             |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : VRAM read latch, read the content of the VRAM
                            pointed by MARR (MARR is auto-incremented after
                            a read of the high byte of VRR).


        +----+-----+------+------------------------------------------------+
        | $2 |  /W | VWR  | VRAM Write Register                            |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : VRAM write latch, data put in this register will
                            be copied to the VRAM location pointed by MAWR
                            (MAWR is auto-incremented after a write to the
                            high byte of VWR).


        +----+-----+------+------------------------------------------------+
        | $5 |  /W |  CR  | Control Register                               |
        +----+-----+------+------------------------------------------------+

                Bit 12-11 : 'IW' Read/write address auto-increment:

                                 00 -> +1
                                 01 -> +32
                                 10 -> +64
                                 11 -> +128

                                 Affect by how much are incremented MARR/MAWR
                                 after an access to VRR/VWR.

                Bit    10 : 'DR' DRAM refresh - always 0.

                Bit 09-08 : 'TE' Display output select - always 00.

                Bit    07 : 'BB' Background enable flag (1 = on).

                Bit    06 : 'SB' Sprites enable flag (1 = on).

                Bit 05-04 : 'EX' External sync - always 00.

                Bit 03-00 : 'IE' Interrupt enable flags (1 = on).

                                 Bit 03 : 'VC' Vertical blanking.
                                 Bit 02 : 'RC' Scanline match (see RCR).
                                 Bit 01 : 'OV' Sprite overflow, more than 16
                                               sprites on a scanline.
                                 Bit 00 : 'CC' Collision detection (between
                                               sprite #0 and any other
                                               sprites).


        +----+-----+------+------------------------------------------------+
        | $6 |  /W | RCR  | Raster Counter Register                        |
        +----+-----+------+------------------------------------------------+

                Bit 09-00 : 'RCR' Scanline index on which an interrupt
                                  should be raised (the first scanline of
                                  the display is scanline number 64).


        +----+-----+------+------------------------------------------------+
        | $7 |  /W | BXR  | Background X scroll Register                   |
        +----+-----+------+------------------------------------------------+

                Bit 09-00 : 'BXR' Horizontal screen offset in the virtual BG
                                  map. Each time the VDC renders a scanline
                                  it gets the display starting X position from
                                  this register. Some pretty nice effects can
                                  be done by just changing this register every
                                  scanline: distortion, sine scroll, etc...


        +----+-----+------+------------------------------------------------+
        | $8 |  /W | BYR  | Background Y scroll Register                   |
        +----+-----+------+------------------------------------------------+

                Bit 08-00 : 'BYR' Vertical screen offset in the virtual BG
                                  map. Same principle as 'BXR' but for the
                                  vertical offset.


        +----+-----+------+------------------------------------------------+
        | $9 |  /W | MWR  | Memory access Width Register                   |
        +----+-----+------+------------------------------------------------+

                Bit    07 : 'CM' CG mode - always 0.

                Bit 06-04 : 'SCREEN' Size of the virtual BG map:

                                 000 -  32 x 32
                                 001 -  64 x 32
                                 010 - 128 x 32
                                 011 - 128 x 32
                                 100 -  32 x 64
                                 101 -  64 x 64
                                 110 - 128 x 64
                                 111 - 128 x 64

                Bit 03-02 : 'SM' Sprite access width Mode - always 00.

                Bit 01-00 : 'VM' VRAM access width mode - always 00.


        +----+-----+------+------------------------------------------------+
        | $A |  /W | HSR  | Horizontal Sync Register                       |
        +----+-----+------+------------------------------------------------+

                Bit 14-08 : 'HDS' Horizontal display start position -1.

                Bit 04-00 : 'HSW' Horizontal sync pulse width.


        +----+-----+------+------------------------------------------------+
        | $B |  /W | HDR  | Horizontal Display Register                    |
        +----+-----+------+------------------------------------------------+

                Bit 14-08 : 'HDE' Horizontal display end position -1.

                Bit 06-00 : 'HDW' Horizontal display width -1.


        +----+-----+------+------------------------------------------------+
        | $C |  /W | VPR  | Vertical Sync Register                         |
        +----+-----+------+------------------------------------------------+

                Bit 15-08 : 'VDS' Vertical display start position -2.

                Bit 04-00 : 'VSW' Vertical sync pulse width.


        +----+-----+------+------------------------------------------------+
        | $D |  /W | VDW  | Vertical Display Register                      |
        +----+-----+------+------------------------------------------------+

                Bit 08-00 : 'VDW' Vertical display width -1.


        +----+-----+------+------------------------------------------------+
        | $E |  /W | VCR  | Vertical Display End Position Register         |
        +----+-----+------+------------------------------------------------+
                   
                Bit 07-00 : 'VCR' Vertical display end position.


        +----+-----+------+------------------------------------------------+
        | $F |  /W | DCR  | DMA Control Register                           |
        +----+-----+------+------------------------------------------------+

                Bit    04 : 'DSR'  VRAM to SATB auto-transfer enable flag
                                   (1 = on).

                Bit    03 : 'DI/D' Destination address direction, '1' to
                                   decrement and '0' to increment.

                Bit    02 : 'SI/D' Source address direction, '1' to
                                   decrement and '0' to increment.

                Bit    01 : 'DVC'  VRAM to VRAM end of transfer interrupt
                                   enable flag (1 = on).

                Bit    00 : 'DSC'  VRAM to SATB end of transfer interrupt
                                   enable flag (1 = on).


        +----+-----+------+------------------------------------------------+
        |$10 |  /W | SOUR | DMA Source Address Register                    |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : Source address for VRAM to VRAM DMA transfer.


        +----+-----+------+------------------------------------------------+
        |$11 |  /W | DESR | DMA Destination Address Register               |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : Destination address for VRAM to VRAM DMA transfer.


        +----+-----+------+------------------------------------------------+
        |$12 |  /W | LENR | DMA Block Length Register                      |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : Length in words of the VRAM to VRAM DMA transfer.
                            Writing to the high byte of this register will
                            auto-start the DMA transfer.


        +----+-----+------+------------------------------------------------+
        |$13 |  /W |DVSSR | VRAM-SATB Source Address Register              |
        +----+-----+------+------------------------------------------------+

                Bit 15-00 : Source address for the VRAM to SATB DMA transfer.
                            Writing to this register will auto-start the
                            DMA at the next vertical sync, even if the DSR
                            bit in DCR is not set, however, the transfer will
                            be repeated every vertical sync only if the DSR
                            bit is set.


---

